1. Technical Field
The disclosures herein relate to a semiconductor memory apparatus and, more particularly, to an on-die termination circuit in a semiconductor memory apparatus.
2. Related Art
Generally, when one bus line having a first impedance meets with another bus line having a second impedance different from the first impedance, a signal loss occurs due to the impedance mismatch. An impedance matching operation can be performed to prevent the signal loss. Such an impedance matching operation is called “On-Die Termination.”
As shown in FIG. 1, a conventional on-die termination circuit in a semiconductor memory apparatus includes a first D/A converter 10, a first comparator 20, a first counter 30, a second D/A converter 40, a second comparator 50, a second counter 60, a pulse generator 70, a first register 80 and a second resistor 90.
The first D/A converter 10 outputs a first voltage VCOMP_P, which corresponds to a first code (PCODE<0:4>), in response to an enable signal (EN). The first comparator 20 compares the first voltage VCOMP_P with a reference voltage VREF in response to a first pulse (CPOUTP<0:1>) and then outputs a first comparison result signal (COMP_OUTP). The level of the reference voltage VREF can be VDDQ/2. VDDQ is an external power source used for data I/O. The first counter 30 up or down counts the first code (PCODE<0:4>) according to a first count pulse (CNT_PULSEP) so as to correspond to the first comparison result signal (COMP_OUTP). The first register 80 stores the first code (PCODE<0:4>) in response to a code storage pulse (2nd_COMP). The second D/A converter 40 outputs a second voltage VCOMP_N, which corresponds to a second code (NCODE<0:4>), in response to the enable signal (EN).
The second comparator 50 compares the second voltage VCOMP_N with the reference voltage VREF in response to a second pulse (CPOUTN<0:1>) to output a second comparison result signal (COMP-OUTN). In similar to the first counter 30, the second counter 60 also up or down counts the second code (NCODE<0:4>) according to a second count pulse (CNT_PULSEN), so as to correspond to the second comparison result signal (COMP-OUTN). The second register 90 stores the second code (NCODE<0:4>) in response to the code storage pulse (2nd_COMP). The pulse generator 70 generates the first pulse (CPOUTP<0:1>), the second pulse (CPOUTN<0:1>), the first count pulse (CNT_PULSEP), the second count pulse (CNT_PULSEN) and the code storage pulse (2nd_COMP) in response to the enable signal (EN).
The operation of a conventional on-die termination circuit will be described below referring to FIGS. 1 and 2. First, the pulse generator 70 generates the first pulse (CPOUTP<0>) and the second pulse (CPOUTN<0>) after a predetermined time of t1 from the activation of the enable signal (EN).
Then, the first comparator 20 compares the first voltage VCOMP_P with the reference voltage VREF in response to the first pulse (CPOUTP<0>), and the second comparator 50 compares the second voltage VCOMP_N with the reference voltage VREF in response to the second pulse (CPOUTN<0>).
After a predetermined time of t1+t2, the pulse generator 70 generates the first pulse (CPOUTP<1>) and the second pulse (CPOUTN<1>).
The first comparator 20 outputs the first comparison result signal (COMP_OUTP) in response to the first pulse (CPOUTP<1>), and the second comparator 50 outputs the second comparison result signal (COMP-OUTN) in response to the second pulse (CPOUTN<1>). After a predetermined time of t1+t2+t3, the pulse generator 70 generates the first count pulse (CNT_PULSEP) and the second count pulse (CNT_PULSEN).
The first counter 30 counts the first code (PCODE<0:4>) up or down, using first count pulse (CNT_PULSEP) in response to the first comparison result signal (COMP_OUTP). The second counter 60 also counts the second code (NCODE<0:4>) up or down, using the second count pulse (CNT_PULSEN) in response to the second comparison result signal (COMP-OUTN). The pulse generator 70 generates the code storage pulse (2nd_COMP) at the start of the second code counting operation and the code storage pulse (2nd_COMP) is deactivated at the termination of the second code counting operation.
The first register 80 stores the first code (PCODE<0:4>) outputted from the first counter 30 and the second register 90 stores the second code (NCODE<0:4>) outputted from the second counter 60 according to the deactivation of the code storage pulse (2nd_COMP). Thus, the on-die termination operation has been finished.
However, as shown in FIG. 3, in the conventional on-die termination circuit, since there exists an offset voltage VOS in the first comparator 20 and the second comparator 50, the level of the reference voltage VREF can be VDDQ/2±VOS. Thus, the first comparison result signal (COMP_OUTP) or the second comparison result signal (COMP_OUTN) can be changed in a high or low level according to the level change of the reference voltage VREF. That is, the first comparison result signal (COMP_OUTP) or the second comparison result signal (COMP_OUTN) can be output with an abnormal value.
If the change value of the first comparison result signal (COMP_OUTP) or the second comparison result signal (COMP_OUTN) for an LSB (Least Significant Bit) code value has a voltage level of VLSB, then the value of the first comparison result signal (COMP_OUTP) or the second comparison result signal (COMP_OUTN) performs a final control has three levels between the maximum value of VDDQ/2+VOS+VLSB and the minimum value of VDDQ/2-VOS-VLSB.
As described above, a conventional on-die termination circuit in a semiconductor memory apparatus has a problem in that a result value produced by the comparison of a voltage according to a code and a reference voltage is not fixed due to an internal offset voltage and is changed at the start and due to termination timings of an on-die termination operation so that a final on-die termination code value can have an erroneous value. If the code value is continuously changed into an erroneous value, then the impedance of a circuitry using the code value, for example, a driver, is also continuously changed to an erroneous value.